A memory device is under developing, which includes memory cells disposed three-dimensionally. For example, a NAND type memory device includes a plurality of electrode layers stacked, and semiconductor pillars provided in the memory holes respectively. The memory holes extend through the plurality of electrode layers in a stacking direction, and the respective semiconductor pillars extend in a memory hole. Memory cells are provided in portions where a semiconductor pillar crosses the electrode layers, and the memory cells are disposed along the semiconductor pillar. In such a memory device, it is possible to enlarge the storage capacity by increasing the number of electrode layers stacked, and increasing the number of memory holes by shrinking. However, there may be limits in increasing the numbers of the memory holes and the electrode layers under the restricted size of the memory device chip.